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SystemVerilog for Design—A Guide to Using SystemVerilog for Hardware Design and Modeling, Second Edition

SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, Second Edition

by Stuart Sutherland, Simon Davidmann and Peter Flake

2006 (436 pages)

ISBN:9780387333991

Reflecting the syntax and semantic changes to the SystemVerilog language, this text explains the SystemVerilog "packages," summarizes the synthesis guidelines presented throughout, and contains code examples using the latest version of the tools.

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Table of Contents

SystemVerilog for Design—A Guide to Using SystemVerilog for Hardware Design and Modeling, Second Edition
List of Examples
Foreword
Preface
Chapter 1	-	Introduction to SystemVerilog
Chapter 2	-	SystemVerilog Declaration Spaces
Chapter 3	-	SystemVerilog Literal Values and Built-in Data Types
Chapter 4	-	SystemVerilog User-Defined and Enumerated Types
Chapter 5	-	SystemVerilog Arrays, Structures and Unions
Chapter 6	-	SystemVerilog Procedural Blocks, Tasks and Functions
Chapter 7	-	SystemVerilog Procedural Statements
Chapter 8	-	Modeling Finite State Machines with SystemVerilog
Chapter 9	-	SystemVerilog Design Hierarchy
Chapter 10	-	SystemVerilog Interfaces
Chapter 11	-	A Complete Design Modeled with SystemVerilog
Chapter 12	-	Behavioral and Transaction Level Modeling
Appendix A	-	The SystemVerilog Formal Definition (BNF)
Appendix B	-	Verilog and SystemVerilog Reserved Keywords
Appendix C	-	A History of SUPERLOG, the Beginning of SystemVerilog