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Low Power Methodology Manual—For System-on-Chip Design

Low Power Methodology Manual: For System-on-Chip Design

by Michael Keating et al.

2007 (302 pages)

ISBN:9780387718187

Taking a practical approach, rather than a theoretical approach, this book describes a number of the techniques designers can use to reduce the power consumption of complex SoC designs.

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Table of Contents

Low Power Methodology Manual—For System-on-Chip Design
Preface
Chapter 1	-	Introduction
Chapter 2	-	Standard Low Power Methods
Chapter 3	-	Multi-Voltage Design
Chapter 4	-	Power Gating Overview
Chapter 5	-	Designing Power Gating
Chapter 6	-	Architectural Issues for Power Gating
Chapter 7	-	A Power Gating Example
Chapter 8	-	IP Design for Low Power
Chapter 9	-	Frequency and Voltage Scaling Design
Chapter 10	-	Examples of Voltage and Frequency Scaling Design
Chapter 11	-	Implementing Multi-Voltage, Power Gated Designs
Chapter 12	-	Physical Libraries
Chapter 13	-	Retention Register Design
Chapter 14	-	Design of the Power Switching Network
Appendix A	-	Sleep Transistor Design
Appendix B	-	UPF Command Syntax
Glossary
Bibliography