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Digital Design with RTL Design, VHDL, and Verilog, Second Edition | by Frank Vahid | 2011 | ISBN: 9780470531082. Digital Electronic Engineering Books. Register-Transfer Level (RTL) Design. Hardware Description Languages

May 18th, 2011 | by kutenk |

Digital Design with RTL Design, VHDL, and Verilog, Second Edition
by Frank Vahid
2011 (592 pages)
ISBN:9780470531082
Offering a modern, updated approach to digital design, this much-needed book reviews basic design fundamentals before diving into specific details of design optimization.
Digital Design with RTL Design, VHDL, and Verilog, Second Edition
Preface
TO STUDENTS ABOUT TO STUDY DIGITAL DESIGN
TO INSTRUCTORS OF DIGITAL DESIGN
HOW TO USE THIS BOOK
ACKNOWLEDGEMENTS
ABOUT THE COVER
ABOUT THE AUTHOR

Chapter 1 – Introduction
1.1: DIGITAL SYSTEMS IN THE WORLD AROUND US
1.2: THE WORLD OF DIGITAL SYSTEMS
1.3: IMPLEMENTING DIGITAL SYSTEMS: MICROPROCESSORS VERSUS DIGITAL CIRCUITS
1.4: ABOUT THIS BOOK
1.5: EXERCISES

Chapter 2 – Combinational Logic Design
2.1: INTRODUCTION
2.2: SWITCHES
2.3: THE CMOS TRANSISTOR
2.4: BOOLEAN LOGIC GATES—BUILDING BLOCKS FOR DIGITAL CIRCUITS
2.5: BOOLEAN ALGEBRA
2.6: REPRESENTATIONS OF BOOLEAN FUNCTIONS
2.7: COMBINATIONAL LOGIC DESIGN PROCESS
2.8: MORE GATES
2.9: DECODERS AND MUXES
2.10: ADDITIONAL CONSIDERATIONS
2.11: COMBINATIONAL LOGIC OPTIMIZATIONS AND TRADEOFFS (SEE SECTION 6.2)
2.12: COMBINATIONAL LOGIC DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES (SEE SECTION 9.2)
2.13: CHAPTER SUMMARY
2.14: EXERCISES

Chapter 3 – Sequential Logic Design—Controllers
3.1: INTRODUCTION
3.2: STORING ONE BIT—FLIP-FLOPS
3.3: FINITE-STATE MACHINES (FSMS)
3.4: CONTROLLER DESIGN
3.5: MORE ON FLIP-FLOPS AND CONTROLLERS
3.6: SEQUENTIAL LOGIC OPTIMIZATIONS AND TRADEOFFS (SEE SECTION 6.3)
3.7: SEQUENTIAL LOGIC DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES (SEE SECTION 9.3)
3.8: PRODUCT PROFILE—PACEMAKER
3.9: CHAPTER SUMMARY
3.10: EXERCISES

Chapter 4 – Datapath Components
4.1: INTRODUCTION
4.2: REGISTERS
4.3: ADDERS
4.4: COMPARATORS
4.5: MULTIPLIER—ARRAY-STYLE
4.6: SUBTRACTORS AND SIGNED NUMBERS
4.7: ARITHMETIC-LOGIC UNITS—ALUS
4.8: SHIFTERS
4.9: COUNTERS AND TIMERS
4.10: REGISTER FILES
4.11: DATAPATH COMPONENT TRADEOFFS (SEE SECTION 6.4)
4.12: DATAPATH COMPONENT DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES (SEE SECTION 9.4)
4.13: PRODUCT PROFILE: AN ULTRASOUND MACHINE
4.14: CHAPTER SUMMARY
4.15: EXERCISES

Chapter 5 – Register-Transfer Level (RTL) Design
5.1: INTRODUCTION
5.2: HIGH-LEVEL STATE MACHINES
5.3: RTL DESIGN PROCESS
5.4: MORE RTL DESIGN
5.5: DETERMINING CLOCK FREQUENCY
5.6: BEHAVIORAL-LEVEL DESIGN: C TO GATES (OPTIONAL)
5.7: MEMORY COMPONENTS
5.8: QUEUES (FIFOs)
5.9: MULTIPLE PROCESSORS
5.10: HIERARCHY—A KEY DESIGN CONCEPT
5.11: RTL DESIGN OPTIMIZATIONS AND TRADEOFFS (SEE SECTION 6.5)
5.12: RTL DESIGN USING HARDWARE DESCRIPTION LANGUAGES (SEE SECTION 9.5)
5.13: PRODUCT PROFILE: CELL PHONE
5.14: CHAPTER SUMMARY
5.15: EXERCISES

Chapter 6 – Optimizations and Tradeoffs
6.1: INTRODUCTION
6.2: COMBINATIONAL LOGIC OPTIMIZATIONS AND TRADEOFFS
6.3: SEQUENTIAL LOGIC OPTIMIZATIONS AND TRADEOFFS
6.4: DATAPATH COMPONENT TRADEOFFS
6.5: RTL DESIGN OPTIMIZATIONS AND TRADEOFFS
6.6: MORE ON OPTIMIZATIONS AND TRADEOFFS
6.7: PRODUCT PROFILE: DIGITAL VIDEO PLAYER/RECORDER
6.8: CHAPTER SUMMARY
6.9: EXERCISES

Chapter 7 – Physical Implementation on ICs
7.1: INTRODUCTION
7.2: MANUFACTURED IC TYPES
7.3: OFF-THE-SHELF PROGRAMMABLE IC TYPE—FPGA
7.4: OTHER OFF-THE-SHELF IC TYPES
7.5: IC TRADEOFFS, TRENDS, AND COMPARISONS
7.6: PRODUCT PROFILE: GIANT LED-BASED VIDEO DISPLAY WITH FPGAS
7.7: CHAPTER SUMMARY
7.8: EXERCISES

Chapter 8 – Programmable Processors
8.1: INTRODUCTION
8.2: BASIC ARCHITECTURE
8.3: A THREE-INSTRUCTION PROGRAMMABLE PROCESSOR
8.4: A SIX-INSTRUCTION PROGRAMMABLE PROCESSOR
8.5: EXAMPLE ASSEMBLY AND MACHINE PROGRAMS
8.6: FURTHER EXTENSIONS TO THE PROGRAMMABLE PROCESSOR
8.7: CHAPTER SUMMARY
8.8: EXERCISES

Chapter 9 – Hardware Description Languages
9.1: INTRODUCTION
9.2: COMBINATIONAL LOGIC DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES
9.3: SEQUENTIAL LOGIC DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES
9.4: DATAPATH COMPONENT DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES
9.5: RTL DESIGN USING HARDWARE DESCRIPTION LANGUAGES
9.6: CHAPTER SUMMARY
9.7: EXERCISES

Appendix A – Boolean Algebras
A.1: BOOLEAN ALGEBRA
A.2: SWITCHING ALGEBRA
A.3: IMPORTANT THEOREMS IN BOOLEAN ALGEBRA
A.4: OTHER EXAMPLES OF BOOLEAN ALGEBRAS
A.5: FURTHER READINGS

Appendix B – Additional Topics in Binary Number Systems
B.1: INTRODUCTION
B.2: REAL NUMBER REPRESENTATION
B.3: FIXED POINT ARITHMETIC
B.4: FLOATING POINT REPRESENTATION
B.5: EXERCISES

Appendix C – Extended RTL Design Example
C.1: INTRODUCTION
C.2: DESIGNING THE SODA DISPENSER CONTROLLER
C.3: UNDERSTANDING THE BEHAVIOR OF THE SODA DISPENSER CONTROLLER AND DATAPATH

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