Three-Dimensional Integrated Circuit Design | by Vasilis F. Pavlidis and Eby G. Friedman | 2009 | ISBN: 9780123743435. Manufacturing of 3-D Packaged Systems. 3-D Integrated Circuit Fabrication Technologies. Physical Design Techniques for 3-D ICs. THREE-DIMENSIONAL NETWORKS-ON-CHIP
Three-Dimensional Integrated Circuit Design
by Vasilis F. Pavlidis and Eby G. Friedman
2009 (324 pages)
ISBN:9780123743435
Covering all of the technological and design aspects of this emerging design paradigm, this comprehensive reference and practical design guide provides a sound foundation for the design of three-dimensional integrated circuits.
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Three-Dimensional Integrated Circuit Design
Preface
OVERVIEW
ACKNOWLEDGMENTS
Chapter 1 – Introduction
OVERVIEW
1.1: FROM THE INTEGRATED CIRCUIT TO THE COMPUTER
1.2: INTERCONNECTS, AN OLD FRIEND
1.3: THREE-DIMENSIONAL OR VERTICAL INTEGRATION
1.4: BOOK ORGANIZATION
Chapter 2 – Manufacturing of 3-D Packaged Systems
2.1: THREE-DIMENSIONAL INTEGRATION
2.2: SYSTEM-ON-PACKAGE
2.3: TECHNOLOGIES FOR SYSTEM-IN-PACKAGE
2.4: COST ISSUES FOR 3-D INTEGRATED SYSTEMS
2.5: SUMMARY
Chapter 3 – 3-D Integrated Circuit Fabrication Technologies
OVERVIEW
3.1: MONOLITHIC 3-D ICs
3.2: 3-D ICs WITH THROUGH SILICON (TSV) OR INTERPLANE VIAS
3.3: CONTACTLESS 3-D ICs
3.4: VERTICAL INTERCONNECTS FOR 3-D ICs
3.5: SUMMARY
Chapter 4 – Interconnect Prediction Models
OVERVIEW
4.1: INTERCONNECT PREDICTION MODELS FOR 2-D CIRCUITS
4.2: INTERCONNECT PREDICTION MODELS FOR 3-D ICs
4.3: PROJECTIONS FOR 3-D ICs
4.4: SUMMARY
Chapter 5 – Physical Design Techniques for 3-D ICs
5.1: FLOORPLANNING TECHNIQUES
5.2: PLACEMENT TECHNIQUES
5.3: ROUTING TECHNIQUES
5.4: LAYOUT TOOLS
5.5: SUMMARY
Chapter 6 – Thermal Management Techniques
OVERVIEW
6.1: THERMAL ANALYSIS OF 3-D ICs
6.2: THERMAL MANAGEMENT TECHNIQUES WITHOUT THERMAL VIAS
6.3: THERMAL MANAGEMENT TECHNIQUES EMPLOYING THERMAL VIAS
6.4: SUMMARY
Chapter 7 – Timing Optimization for Two-Terminal Interconnects
OVERVIEW
7.1: INTERPLANE INTERCONNECT MODELS
7.2: TWO-TERMINAL NETS WITH A SINGLE-INTERPLANE VIA
7.3: TWO-TERMINAL INTERCONNECTS WITH MULTIPLE-INTERPLANE VIAS
7.4: SUMMARY
Chapter 8 – Timing Optimization for Multiterminal Interconnects
8.1: TIMING-DRIVEN VIA PLACEMENT FOR INTERPLANE INTERCONNECT TREES
8.2: MULTITERMINAL INTERCONNECT VIA PLACEMENT HEURISTICS
8.3: VIA PLACEMENT ALGORITHMS FOR INTERCONNECT TREES
8.4: VIA PLACEMENT RESULTS AND DISCUSSION
8.5: SUMMARY
Chapter 9 – 3-D Circuit Architectures
OVERVIEW
9.1: CLASSIFICATION OF WIRE-LIMITED 3-D CIRCUITS
9.2: THREE-DIMENSIONAL MICROPROCESSORS AND MEMORIES
9.3: THREE-DIMENSIONAL NETWORKS-ON-CHIP
9.4: THREE-DIMENSIONAL FPGAs
9.5: SUMMARY
Chapter 10 – Case Study: Clock Distribution Networks for 3-D ICs
OVERVIEW
10.1: MIT LINCOLN LABORATORIES 3-D IC FABRICATION TECHNOLOGY
10.2: 3-D CIRCUIT ARCHITECTURE
10.3: CLOCK SIGNAL DISTRIBUTION IN 3-D CIRCUITS
10.4: EXPERIMENTAL RESULTS
10.5: SUMMARY
Chapter 11 – Conclusions
Appendix A – Enumeration of Gate Pairs in a 3-D IC
Appendix B – Formal Proof of Optimum Single Via Placement
Appendix C – Proof of the Two-Terminal Via Placement Heuristic
Appendix D – Proof of Condition for Via Placement of Multiterminal Nets
References
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