Practical Design Verification | by Dhiraj K. Pradhan and Ian G. Harris | 2009 | ISBN: 9780521859721. Transaction-Level System Modeling. System Debugging Strategies. Model Checking Techniques. Techniques for Higher-Level Design Descriptions
Practical Design Verification
by Dhiraj K. Pradhan and Ian G. Harris
2009 (288 pages)
ISBN:9780521859721
Offering a theoretical and practical understanding of the key issues involved, this book will help to improve design efficiency and reduce costs with this guide to formal and simulation-based functional verification.
Get this Book by clicking below:
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Practical Design Verification
Chapter 1 – Model Checking and Equivalence Checking
1.1: Introduction
1.2: Techniques for Boolean Reasoning
1.3: Model Checking Techniques
1.4: Equivalence-Checking Techniques
1.5: Techniques for Higher-Level Design Descriptions
1.6: References
Chapter 2 – Transaction-Level System Modeling
Overview
2.1: Taxonomy for TLMs
2.2: Estimation-Oriented TLMs
2.3: Synthesis-Oriented TLMs
2.4: Related Work on TLMs
2.5: Summary and Conclusions
2.6: References
Chapter 3 – Response Checkers, Monitors, and Assertions
3.1: Introduction
3.2: Testbench Verification Components
3.3: Assertion-Based Verification
3.4: Assertion-Based Bus Monitor Example
3.5: Summary
3.6: References
Chapter 4 – System Debugging Strategies
4.1: Introduction
4.2: Debugging Tools
4.3: Debugging Commands
4.4: Functional Debugging
4.5: Performance-Oriented Debugging
4.6: Summary
4.7: References
Chapter 5 – Test Generation and Coverage Metrics
5.1: Introduction
5.2: Coverage Metrics
5.3: Classification of Coverage Metrics
5.4: Coverage Metrics and Abstraction Levels of Design
5.5: Stimuli Generation Methods
5.6: Acknowledgements
5.7: References
Chapter 6 – SystemVerilog and Vera in a Verification Flow
6.1: Introduction
6.2: Testbench Components
6.3: Verification Plan
6.4: Case Study
6.5: Summary
6.6: References
Chapter 7 – Decision Diagrams for Verification
7.1: Introduction
7.2: Decision Diagrams
7.3: Binary Moment Diagrams (BMDs)
7.4: Taylor Expansion Diagrams (TEDs)
7.5: Represention of Multiple-Output Functions Over Finite Fields
7.6: Acknowledgements
7.7: References
Chapter 8 – Boolean Satisfiability and EDA Applications
8.1: Introduction
8.2: Definitions
8.3: Extensions of SAT
8.4: Applications of SAT in EDA
8.5: Conclusions
8.6: Acknowledgement
8.7: References
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