Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design | by Deepak A. Mathaikutty and Sandeep K. Shukla | 2009 | ISBN: 9781596934245. Modeling and Validation Environment (MMV). Design Fault Directed Test Generation. Model-Driven System-Level Validation
Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design
by Deepak A. Mathaikutty and Sandeep K. Shukla
2009 (310 pages)
ISBN:9781596934245
Addressing key factors related to the use of reusable verification IPs for a ‘write once, use many times’ verification strategy, this book covers the essential issues associated with fast and effective integration of reusable design components into a SoC.
Get this Book by clicking below:
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Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design
Preface
Overview
References
Chapter 1 – Introduction
Overview
1.1: Ongoing Efforts in Design IP Reuse
1.2: Ongoing Efforts in Verification IP Reuse
1.3: Essential Issues with IP Reuse
1.4: Metamodeling Approach to Reuse
1.5: Problem Statement
1.6: Research Contributions
1.7: Tools and Techniques Developed
References
Chapter 2 – Background
2.1: Metamodeling
2.2: Component Composition Framework
2.3: Reflection and Introspection (R-I)
2.4: SystemC
2.5: Model-Driven Validation
2.6: Test Generation
2.7: Coverage-Directed Test Generation
References
Chapter 3 – Related Work
3.1: Component Composition Framework
3.2: Component-Based Software Design Environments
3.3: IP Interfacing Standards
3.4: Existing Tools for Structural Reflection
3.5: Architecture Description Languages
3.6: Test Generation
References
Part I – Design Reuse
Chapter 4 – A Metamodel for Component Composition
Overview
4.1: CC Language, Metamodel, and Model
4.2: CC Analysis and Translation
4.3: Case Studies
4.4: Design Experience and Summary
References
Chapter 5 – IP Reflection and Selection
Overview
5.1: Metadata for IP Composition
5.2: Metadata on a SystemC IP Specification
5.3: Tools and Methodology
5.4: IP Selection
5.5: Case Study
5.6: Summary
References
Chapter 6 – Typing Problems in IP Composition
Overview
6.1: MCF Type Definitions
6.2: Type Resolution in MCF
6.3: Comparative Study
6.4: Case Study
6.5: Summary
References
Chapter 7 – IP Composition
Overview
7.1: MCF Ingredients
7.2: Handling Generic IPS
7.3: Interaction Pattern
7.4: Case Study
7.5: Summary
References
Chapter 8 – Checker Generation for IP Verification
8.1: Enhanced Design Flow
8.2: Enhanced Modeling Framework
8.3: Interaction Console
8.4: Conclusion
References
Part II – Verification Reuse
Chapter 9 – A Metamodel for Microprocessors
9.1: Modeling and Validation Environment (MMV)
9.2: Simulator Generation
9.3: Test Generation
9.4: Case Study: Modeling Vespa in MMV
9.5: Summary
References
Chapter 10 – Design Fault Directed Test Generation
Overview
10.1: Motivation
10.2: Modeling and Test Generation
10.3: Coverage Constraints
10.4: Results
10.5: Summary
References
Chapter 11 – Model-Driven System-Level Validation
Overview
11.1: Test Generation Methodology
11.2: Systemc Validation
11.3: Case Study
11.4: Summary
References
Chapter 12 – Conclusion and Future Work
12.1: Summary
12.2: Future Work
References
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