Integrated Interconnect Technologies for 3D Nanoelectronic Systems | by Muhannad S. Bakir and James D. Meindl (eds) | 2009 | ISBN: 9781596932463. Integrated Microsystems Books. Revolutionary Silicon Ancillary Technologies. Electrical Signaling Techniques. Active Microfluidic Cooling of Integrated Circuits
Integrated Interconnect Technologies for 3D Nanoelectronic Systems
by Muhannad S. Bakir and James D. Meindl (eds)
2009 (550 pages)
ISBN:9781596932463
Bringing readers up to speed with the latest heat removal technologies, this book explores interconnect structures, materials, and packages for achieving high-bandwidth off-chip electrical communication.
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Integrated Interconnect Technologies for 3D Nanoelectronic Systems
Foreword
Preface
Chapter 1 – Revolutionary Silicon Ancillary Technologies for the Next Era of Gigascale Integration
1.1: Introduction
1.2: The Role of Innovation in Sustaining Moore’s Law
1.3: Silicon Technology: The Three Eras
1.4: Need for Disruptive Silicon Ancillary Technologies: Third Era of Silicon Technology
1.5: Conclusion
References
Chapter 2 – Chip-Package Interaction and Reliability Impact on Cu/Low-k Interconnects
2.1: Introduction
2.2: Experimental Techniques
2.3: Mechanics of Cohesive and Interfacial Fracture in Thin Films
2.4: Modeling of Chip-Packaging Interactions
2.5: Energy Release Rate Under Chip-Package Interactions
2.6: Effect of Interconnect Scaling and Ultralow-k Integration
2.7: Summary
Acknowledgments
References
Chapter 3 – Mechanically Compliant I/O Interconnects and Packaging
3.1: Introduction
3.2: Compliant I/O Requirements
3.3: Overview of Various Compliant Interconnect Technologies
3.4: Design and Analysis of Compliant Interconnects
3.5: Case Study on Trade-Offs in Electrical/Mechanical Characteristics of Compliant Interconnects
3.6: Reliability Evaluation of Compliant Interconnects
3.7: Compliant Interconnects and Low-k Dielectrics
3.8: Assembly of Compliant Interconnects
3.9: Case Studies: Assembly of Sea of Leads and G-Helix Interconnects
3.10: Integrative Solution
3.11: Summary
References
Chapter 4 – Power Delivery to Silicon
4.1: Overview of Power Delivery
4.2: Power Delivery Trends
4.3: The Off-Chip Power Delivery Network
4.4: dc-dc Converter
4.5: Linear Regulator
4.6: Power Delivery for 3D
4.7: Conclusion
References
Chapter 5 – On-Chip Power Supply Noise Modeling for Gigascale 2D and 3D Systems
5.1: Introduction: Overview of the Power Delivery System
5.2: On-Chip Power Distribution Network
5.3: Compact Physical Modeling of the IR-Drop
5.4: Blockwise Compact Physical Models for ?I Noise
5.5: Compact Physical Models for ?I Noise Accounting for Hot Spots
5.6: Analytical Physical Model Incorporating the Impact of 3D Integration
5.7: Conclusion
References
Chapter 6 – Off-Chip Signaling
6.1: Historical Overview of Off-Chip Communication
6.2: Challenges in Achieving High-Bandwidth Off-Chip Electrical Communication
6.3: Electrical Channel Analysis
6.4: Electrical Signaling Techniques
6.5: Circuit Techniques for I/O Drivers/Receivers and Timing Recovery
6.6: Packaging Impact on Off-Chip Communication
6.7: New Interconnect Structures, Materials, and Packages
6.8: Conclusion
References
Chapter 7 – Optical Interconnects for Chip-to-Chip Signaling
7.1: Introduction
7.2: Why Optical Interconnects?
7.3: Cost-Distance Comparison of Electrical and Optical Links
7.4: Chip-Based Optical Interconnects
7.5: Summary, Issues, and Future Directions
7.6: Summary
References
Chapter 8 – Monolithic Optical Interconnects
Overview
8.1: Optical Sources on Si
8.2: Optical Modulators and Resonators on Si
8.3: Optical Detectors on Si
8.4: CMOS-Compatible Optical Waveguides
8.5: Commercialization and Manufacturing
References
Chapter 9 – Limits of Current Heat Removal Technologies and Opportunities
9.1: Introduction
9.2: Thermal Problem at the Data-Center Level
9.3: Emerging Microprocessor Trends and Thermal Implications
9.4: The Thermal Resistance Chain: Challenges and Opportunities
9.5: Thermal Interface Materials Challenges
9.6: Conductive and Fluidic Thermal Spreaders: State of the Art
9.7: Heat-Transfer Coefficient for Various Cooling Technologies
9.8: Air-Cooled Heat Sinks and Alternatives
9.9: Microchannel Heat Sink Design
9.10: Conclusion
References
Chapter 10 – Active Microfluidic Cooling of Integrated Circuits
10.1: Introduction
10.2: Single-Phase Flow Cooling
10.3: Two-Phase Convection in Microchannels
10.4: Modeling
10.5: Pumping Considerations
10.6: Optimal Architectures and 3D IC Considerations
10.7: Future Outlook
10.8: Nomenclature
References
Chapter 11 – Single and 3D Chip Cooling Using Microchannels and Microfluidic Chip I/O Interconnects
11.1: Introduction
11.2: Summary of Microchannel Cooling Technologies for ICs
11.3: Fabrication of On-Chip Microfluidic Heat Sink
11.4: Integration of Microfluidic and Electrical Chip I/O Interconnections
11.5: Flip-Chip Assembly of Die with Electrical and Thermofluidic I/Os
11.6: Thermal Measurements
11.7: Hydraulic Requirement Analysis
11.8: Microfluidic Network to 3D Microsytems
11.9: Conclusion
Acknowledgments
References
Chapter 12 – Carbon Nanotube Electrical and Thermal Properties and Applications for Interconnects
12.1: Introduction
12.2: Carbon Nanotube Growth and Growth Mechanisms
12.3: Carbon Nanotubes for Interconnect Applications
12.4: Thermal Properties of Carbon Nanotubes
12.5: Carbon Nanotubes as Thermal Interface Materials
12.6: Integration of Carbon Nanotubes into Microsystems for Thermal Management
12.7: Summary and Future Needs
References
Chapter 13 – 3D Integration and Packaging for Memory
13.1: Introduction
13.2: Evolution of Memory Technology
13.3: 3D Chip-Stacking Package for Memory
13.4: 3D Device-Stacking Technology for Memory
13.5: Other Technologies
13.6: Conclusion
References
Chapter 14 – 3D Stacked Die and Silicon Packaging with Through-Silicon Vias, Thinned Silicon, and Silicon-Silicon Interconnection Technology
14.1: Introduction
14.2: Industry Advances in Chip Integration
14.3: 2D and 3D Design and Application Considerations
14.4: Through-Silicon Vias
14.5: BEOL, Signal Integrity, and Electrical Characterization
14.6: Silicon-Silicon Interconnections, Microbumps, and Assembly
14.7: Known Good Die and Reliability Testing
14.8: 3D Modeling
14.9: Trade-Offs in Application Design and Integration
14.10: Summary
Acknowledgments
References
Chapter 15 – Capacitive and Inductive-Coupling I/Os for 3D Chips
15.1: Introduction
15.2: Capacitive-Coupling I/O
15.3: Inductive-Coupling I/O
15.4: Low-Power Design
15.5: High-Speed Design
15.6: High-Density Design
15.7: Challenges and Opportunities
15.8: Conclusion
References
Chapter 16 – Wafer-Level Testing of Gigascale Integrated Circuits
16.1: Introduction
16.2: Wafer-Level Testing of Gigascale Integrated Circuits
16.3: Probe Cards for Wafer-Level Testing
16.4: What Lies Ahead
16.5: Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects
16.6: Summary
References
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