Hybrid CMOS Single-Electron-Transistor Device and Circuit Design | by Santanu Mahapatra and Adrian Mihai Ionescu | ISBN: 9781596930698. CMOS Scaling and Single Electronics. Computer-Aided Design Tools for SET Simulation. SET and MOSFET Modeling Techniques

January 9, 2010 by kutenk
Filed under: Engineering Books

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

by Santanu Mahapatra and Adrian Mihai Ionescu
2006 (237 pages)
ISBN:9781596930698

Offering a thorough understanding of the pros and cons of digital SETs, this cutting-edge resource provides professionals with the conceptual framework and specific strategies for CMSO-SET hybrid circuit design.

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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

Preface
Chapter 1 – Introduction: CMOS Scaling and Single Electronics
1.1: CMOS Scaling Limits
1.2: Emerging Nanotechnologies: Life After CMOS
1.3: Single-Electron Transistors—An Overview
1.4: Short History
References

Chapter 2 – Compact Modeling of SETs
2.1: Computer-Aided Design Tools for SET Simulation
2.2: Orthodox Theory of Single-Electron Tunneling
2.3: Carrier Transport in SET
2.4: Compact Modeling of SET
2.5: Model Verification
2.6: Subthreshold Slope
2.7: Parameter Extraction
2.8: Other SET Models
2.9: SET and MOSFET Modeling Techniques—A Comparison
2.10: Summary
References

Chapter 3 – Single-Electron Transistor Logic
3.1: Single-Electron Memory Versus Logic
3.2: SET Inverter Characteristics
3.3: Analysis of Inverter Characteristics
3.4: Estimation of Power Dissipation
3.5: Propagation Delay of SET Inverter
3.6: Other Single-Electron Logic Gates
3.7: Comparison Between SET and CMOS Logic
3.8: Summary
References

Chapter 4 – Hybridization of CMOS and SET
4.1: Motivation for CMOS-SET Hybridization
4.2: Challenges for CMOS-SET Hybridization
4.3: CMOS-SET Cosimulation and Codesign
4.4: Case Studies of Different Hybrid CMOS-SET Architectures
4.5: SETMOS—Coulomb Blockade Oscillations in the Microampere Range
4.6: Summary
References

Chapter 5 – Few Electron Multiple Valued Logic and Memory Design
5.1: Multiple Value Switching Algebra
5.2: Motivation for MV Logic Design
5.3: Challenges for MVL Circuit Design
5.4: SETMOS Quaternary Logic
5.5: SETMOS Quaternary SRAM
5.6: Summary
References

Chapter 6 – Fabrication of SETs and Compatibility with Silicon CMOS
6.1: Challenges of SET Fabrication
6.2: Single Island SET Fabrication
6.3: Fabrication of Multi-Island SETs
6.4: Fabrication of CNTs and Molecular SETs
6.5: Summary
References

Appendix A – Gibbs Free Energy and Development of MIB Model
A.1: Gibbs Free Energy for Single-Electron Systems
A.2: Calculation of ?G for SET
A.3: Calculation of Drain Current in the MIB Model

Appendix B – Transconductance and Conductance Analysis of the SET
B.1: Transconductance Analysis
B.2: Conductance Analysis

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