Designing Bipolar Transistor Radio Frequency Integrated Circuits | by Allen A. Sweet | ISBN: 9781596931282. RFIC Architectures. InGaP/GaAs HBT Fabrication Technology. Passive Circuit Design. Low-Noise Amplifier Design. Mixer/Modulator Design. Voltage-Controlled Oscillator Design
Designing Bipolar Transistor Radio Frequency Integrated Circuits
by Allen A. Sweet
ISBN:9781596931282
If you’re looking for an in-depth and up-to-date understanding of bipolar transistor RFIC design, this practical resource is dedicated exclusively to RFIC designs based on bipolar technology.
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Designing Bipolar Transistor Radio Frequency Integrated Circuits
Chapter 1 – Introduction
Overview
References
Chapter 2 – Applications
2.1: Cellular/PCS Handsets
2.2: Cellular/PCS Infrastructure
2.3: WLANs
2.4: Bluetooth
2.5: UWB
2.6: WiMax
2.7: Digital TV and Set-Top Boxes
2.8: Cognitive Radio
2.9: Spectrum Allocation in the United States (All Frequencies in Megahertz)
2.10: Physical Layer Standards
References
Chapter 3 – RFIC Architectures
3.1: I/Q Receivers
3.2: I/Q Modulators
3.3: Nonzero IF Receivers
3.4: Zero IF Receivers
3.5: Differential versus Single-Ended Topologies
References
Chapter 4 – InGaP/GaAs HBT Fabrication Technology
4.1: Transistor Structures
4.2: Device Models
4.3: Passive Structures, Their Electrical Models, and Layout Design Rules
4.4: Maximum Electrical Ratings
4.5: CAD Layout Tools
References
Chapter 5 – SiGe HBT Fabrication Technology
5.1: SiGe HBT Transistor Structures
5.2: Transistor Device Models
5.3: Passive Device Structures and Models
5.4: Design Rules
5.5: CAD Layout
References
Chapter 6 – Passive Circuit Design
6.1: Low-Pass Filters
6.2: High-Pass Filters
6.3: Band-Pass Filters
6.4: Differential Filters
6.5: Technology and Substrates
6.6: Splitters/Dividers
6.7: Phase Shifters and Baluns
References
Chapter 7 – Amplifier Design Basics
7.1: Matching Techniques
7.2: Gain Compensation
7.3: Fano’s Limit
7.4: Stability
7.5: Noise Match
7.6: Differential Amplifiers
7.7: Cascode Amplifiers
References
Chapter 8 – Low-Noise Amplifier Design
8.1: Noise Figure Concepts
8.2: Noise Temperature
8.3: Front-end Attenuation and LNAs
8.4: Multistage Noise Figure Contributions
8.5: Circuit Topologies for Low Noise
8.6: Design Example 1: Single-Ended PCS LNA
8.7: Design Example 2: Three-Transistor Hybrid Darlington Differential LNA Using SiGe Technology
References
Chapter 9 – Power Amplifier Design
Overview
9.1: Loadline Concepts
9.2: Maximum Power and Efficiency
9.3: Class AB Power Amplifiers
9.4: Definitions of Nonlinear Performance Metrics
9.5: Adjacent Channel Power Ratio
9.6: Error Vector Magnitude
9.7: Circuit Topologies for PAs
9.8: Matching Circuit Options
9.9: Stability
9.10: Bias Circuits
9.11: Design Example 3: Wideband Gain Block Darlington Amplifier
9.12: Design Example 4: Feedback Power Amplifier Design
References
Chapter 10 – Designing Multistage Amplifiers
10.1: Multistage LNAs
10.2: Multistage Power Amplifiers
10.3: Gain and Power Allocations
10.4: Active Device Sizing
10.5: Design Example 5: A Differential PCS PA
Endnote
References
Chapter 11 – Mixer/Modulator Design
11.1: Mixer Basics
11.2: Diode Mixers
11.3: Single-Balanced Active Multiplying Mixers
11.4: Fully Balanced Active Multiplying Mixers (Gilbert Cell)
11.5: I/Q Mixers
11.6: I/Q Modulators
11.7: Design Example 6: Cellular/PCS Downconverting Mixer RFIC
References
Chapter 12 – Frequency Multiplier Design
12.1: Frequency Doublers
12.2: Frequency Triplers
12.3: Frequency Translators
References
Chapter 13 – Voltage-Controlled Oscillator Design
Overview
13.1: Varactor Diode Basics
13.2: Negative-Resistance Concepts
13.3: Types of Resonators
13.4: Feedback Circuit Topologies for Producing Negative Resistance
13.5: Frequency-Temperature Stability
13.6: Phase Noise
13.7: Quadrature Phase-Shifting Networks
13.8: Ring Oscillators
13.9: Design Example 7: 802.11a (Wi-Fi A) Differential VCO
13.10: Figure of Merit
13.11: Electronic Tuning and a Differential VCO Topology
References
Chapter 14 – Layout Design Strategies
14.1: Minimum Area
14.2: “On-Chip” versus “Off-Chip” Component Decisions
14.3: Minimizing Parasitics
14.4: Testability
14.5: Types of CAD Systems
14.6: Foundry Comparison
14.7: Reticle Assembly
Chapter 15 – RFIC Economics
15.1: Levels of Integration
15.2: Single-Ended versus Differential Topologies
15.3: Process Technology Choices
15.4: Area versus Performance Trade-offs
15.5: Electrical Yield
15.6: Prototype Costs
15.7: Production Costs
Acronyms
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