Design Methodology for RF CMOS Phase Locked Loops | by Guillermo Bistué, Íñigo Adin and Carlos Quemada | 2009 | ISBN: 9781596933835. High-Frequency Divider Architectures and Building Blocks. Design of a Phase Frequency Detector. Design of a Frequency Divider

January 6, 2010 by kutenk
Filed under: Engineering Books 

Design Methodology for RF CMOS Phase Locked Loops

by Guillermo Bistué, Íñigo Adin and Carlos Quemada
2009 (242 pages)
ISBN:9781596933835

Guiding practitioners every step of the way, from specification definition to layout generation, this authoritative resource takes engineers step-by-step through operation principles, design procedures, phase noise analysis, and much more.

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Design Methodology for RF CMOS Phase Locked Loops







Preface
Overview
Acknowledgments

Chapter 1 – Approach to CMOS PLL Design
Overview
1.1: MOS Transistor Basics
1.2: Nonideal and Second-Order Effects in Submicron Technologies
1.3: Impact on PLL Performance
1.4: State of the Art and Challenges in CMOS PLL Design
1.5: PLL Design Flow
1.6: Basic Design Bibliography
References




Chapter 2 – PLL Fundamentals
2.1: Frequency Synthesizer
2.2: Fundamental Figures of Merit of a Frequency Synthesizer
References

Chapter 3 – LC-Tank Integrated Oscillators
Overview
3.1: Functional Description
3.2: Types of LC-Tank Oscillators
3.3: Integrated Passive Elements
3.4: LC-Tank Oscillator Phase Noise
3.5: Designing the Layout of the Oscillator
References

Chapter 4 – Frequency Divider
Overview
4.1: Basic Frequency Dividers
4.2: High-Frequency Divider Architectures and Building Blocks
4.3: High-Frequency Divider-by-2
4.4: Dual-Modulus Prescaler
4.5: Low-Frequency Dividers
4.6: Phase Noise
4.7: Layout Considerations
References

Chapter 5 – Phase Frequency Detector/Phase Detector
Overview
5.1: Multipliers
5.2: Exclusive-OR Logic Gate
5.3: Flip-Flop
5.4: PFD/CP
5.5: Phase Noise of Phase Detectors
5.6: Practical Considerations of Design
5.7: Design of the Layout of the Phase Detector
References

Chapter 6 – Determination of Building Blocks Specifications
Overview
6.1: Initial Requirements
6.2: Architecture Selection
6.3: Ad Hoc Simulation Tool: Simusyn
6.4: Building Block Specification
References



Chapter 7 – Design of a 3.2-GHz CMOS VCO
Overview
7.1: Choice of Architecture of the Oscillator
7.2: Design of the Oscillator
References




Chapter 8 – Design of a Frequency Divider
Overview
8.1: Choice of the Architecture of the Divider
8.2: Design of the Frequency Divider
8.3: Design of the Schematic Circuit of the Divider
8.4: Divisor Layout Generation and Simulation
References

Chapter 9 – Design of a Phase Frequency Detector
Overview
9.1: Choice of the Architecture of the Detector
9.2: Design of the Phase Frequency Detector
References

Chapter 10 – Design of the Complete PLL
Overview
10.1: General Considerations
10.2: Schematic Circuit Design of the Synthesizer
10.3: Layout of the Synthesizer

Chapter 11 – PLL Characterization and Results
11.1: VCO
11.2: Frequency Divider
11.3: Complete PLL
11.4: Result Discussion
References

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