On-Chip Communication Architectures: System on Chip Interconnect | by Sudeep Pasricha and Nikil Dutt | ISBN: 9780123738929. Bus-Based Communication Architectures. Networks-On-Chip Design. On-Chip Interconnect Technologies
On-Chip Communication Architectures: System on Chip Interconnect
by Sudeep Pasricha and Nikil Dutt
ISBN:9780123738929
Presenting a comprehensive reference on concepts, research and trends in on-chip communication architecture design, this book offers a detailed analysis of all popular standards for on-chip communication architectures.
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On-Chip Communication Architectures—System on Chip Interconnect
Preface
Overview
Audience for This Book
How to Use This Book
Chapter 1 – Introduction
1.1: Trends in System-on-Chip Design
1.2: Coping with SoC Design Complexity
1.3: ESL Design Flow
1.4: On-Chip Communication Architectures: A Quick Look
1.5: Book Outline
References
Chapter 2 – Basic Concepts of Bus-Based Communication Architectures
2.1: Terminology
2.2: Characteristics of Bus-Based Communication Architectures
2.3: Data Transfer Modes
2.4: Bus Topology Types
2.5: Physical Implementation of Bus Wires
2.6: Discussion: Buses in the DSM Era
2.7: Summary
References
Chapter 3 – On-Chip Communication Architecture Standards
Overview
3.1: Standard On-Chip Bus-Based Communication Architectures
3.2: Socket-based On-chip Bus Interface Standards
3.3: Discussion: Off-chip Bus Architecture Standards
3.4: Summary
References
Chapter 4 – Models for Performance Exploration
Overview
4.1: Static Performance Estimation Models
4.2: Dynamic (Simulation-based) Performance Estimation Models
4.3: Hybrid Communication Architecture Performance Estimation Approaches
4.4: Summary
References
Chapter 5 – Models for Power and Thermal Estimation
Overview
5.1: Bus Wire Power Models
5.2: Comprehensive Bus Architecture Power Models
5.3: Bus Wire Thermal Models
5.4: Discussion: Pvt Variation-aware Power Estimation
5.5: Summary
References
Chapter 6 – Synthesis of On-Chip Communication Architectures
Overview
6.1: Bus Topology Synthesis
6.2: Bus Protocol Parameter Synthesis
6.3: Bus Topology and Protocol Parameter Synthesis
6.4: Physical Implementation Aware Synthesis
6.5: Memory—Communication Architecture Co-Synthesis
6.6: Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures
6.7: Summary
References
Chapter 7 – Encoding Techniques for On-Chip Communication Architectures
Overview
7.1: Techniques for Power Reduction
7.2: Techniques for Reducing Capacitive Crosstalk Delay
7.3: Techniques for Reducing Power and Capacitive Crosstalk Effects
7.4: Techniques for Reducing Inductive Crosstalk Effects
7.5: Techniques for Fault Tolerance and Reliability
7.6: Summary
References
Chapter 8 – Custom Bus-Based On-Chip Communication Architecture Design
8.1: Split Bus Architectures
8.2: Serial Bus Architectures
8.3: CDMA-based Bus Architectures
8.4: Asynchronous Bus Architectures
8.5: Dynamically Reconfigurable Bus Architectures
8.6: Summary
Further Reading
References
Chapter 9 – On-Chip Communication Architecture Refinement and Interface Synthesis
Overview
9.1: On-chip Communication Architecture Refinement
9.2: Interface Synthesis
9.3: Discussion: Interface Synthesis
9.4: Summary
References
Chapter 10 – Verification and Security Issues in On-Chip Communication Architecture Design
Overview
10.1: Verification of On-Chip Communication Protocols
10.2: Compliance Verification for IP Block Integration
10.3: Basic Concepts Of SoC Security
10.4: Security Support in Standard Bus Protocols
10.5: Communication Architecture Enhancements for Improving SoC Security
10.6: Summary
References
Chapter 11 – Physical Design Trends for Interconnects
Overview
11.1: DSM Interconnect Design
11.2: Low Power, High Speed Circuit Design Techniques
11.3: Global Power Distribution Networks
11.4: Clock Distribution Networks
11.5: 3-D Interconnects
11.6: Summary and Concluding Remarks
References
Chapter 12 – Networks-On-Chip
Overview
12.1: Network Topology
12.2: Switching Strategies
12.3: Routing Algorithms
12.4: Flow Control
12.5: Clocking Schemes
12.6: Quality of Service
12.7: NoC Architectures
12.8: NoC Status and Open Problems
12.9: Summary
Further Reading
References
Chapter 13 – Emerging On-Chip Interconnect Technologies
13.1: Optical Interconnects
13.2: RF/Wireless Interconnects
13.3: CNT Interconnects
13.4: Summary
References
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