Phase-Locked Loop Engineering Handbook for Integrated Circuits | by Stanley Goldman | ISBN: 9781596931541. Elecronic Engineering Books. Behavioral Modeling of PLL with PSPICE. Loop-Component Synthesis. Optimum PLL Design for Low-Phase-Noise Performance.
Phase-Locked Loop Engineering Handbook for Integrated Circuits
by Stanley Goldman
ISBN:9781596931541
Guiding you through design, simulation, and troubleshooting, this easy-to-reference book provides a collection of practical solutions, SPICE listings, simulation techniques, and testing set-ups.
Get this Book by clicking below:
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Phase-Locked Loop Engineering Handbook for Integrated Circuits
Preface
Overview
Book Summary
Chapter 1 – Getting Started with PLLs
1.1: Definition and Operation
1.2: Phase-Lock Loop Literature
1.3: Loop Classifications
1.4: Example Applications
Questions
References
Chapter 2 – System Analysis
2.1: VCO Mathematical Description
2.2: Phase Detector Mathematical Relationship
2.3: PLL Transfer Function and Control-Systems Theory
2.4: Error Tracking
2.1: Type 2, Second-Order Active Loop-to-Servo Terminology
2.6: Loop Stability: Bode Plot Analysis
2.7: Loop Stability: Root-Locus Analysis
2.8: Charge Pump Synthesis Example of Loop-Component Values
2.9: Summary
Questions
References
Chapter 3 – System Requirements
3.1: Noise Basics
3.2: Phase-Noise and Oscillator Theory
3.3: Jitter in PLLs
3.4: Time-Domain Solution
3.5: Acquisition of Lock
3.6: Spurious Signals
3.7: Summary
Questions
References
Appendix 3A: Single-Ended Explanation of Offset Currents
Chapter 4 – Components, Part 1—Dividers and Oscillators
Overview
4.1: Dividers
4.2: Voltage-Controlled Oscillators
4.3: Reference Oscillators
4.4: Summary
Questions
References
Chapter 5 – Components, Part 2—Detectors and other Circuits
Overview
5.1: Phase Detectors
5.2: Lock Detection
5.3: Acquisition Aids
5.4: Charge Pumps
5.5: Design Considerations for Opamps in a PLL
5.6: Differences between Charge Pump and Operational Amplifier Compensation
5.7: Summary
Questions
References
Chapter 6 – Loop-Compensation Synthesis Revisited
Overview
6.1: Ranking Requirements for PLLs
6.2: Loop-Component Synthesis
6.3: Active Compensation and Maximum Capacitor Value
6.4: Sampling-Delay Synthesis
6.5: Fast Switching Time
6.6: Minimum Bandwidth of a PLL
6.7: Maximum-Divide-Ratio Example for Loop-Component Synthesis
6.8: Optimum PLL Design for Low-Phase-Noise Performance
6.9: Summary
Questions
References
Chapter 7 – Test and Measurement
Overview
7.1: Hold-in Range, Lock Range, and Spurious Signals
7.2: Switching Time
7.3: Closed-Loop Bandwidth
7.4: Measurement of Phase Noise
7.5: Testing for Jitter
7.6: Noise Immunity to Injected Signals
7.7: Power-on Switching Time
7.8: Oscillator Open-Loop Test
7.9: Test Equipment
7.10: Troubleshooting PLLs
Questions
References
Chapter 8 – Simulation
8.1: Transistor Level
8.2: Behavioral Modeling of PLL with PSPICE
8.3: Difference-Equation Modeling of PLLs
Questions
References
Chapter 9 – Applications and Extensions
Overview
9.1: Design Trade-Offs in Frequency Generation with PLLs
9.2: Clock Recovery
9.3: Effect of Phase Noise on A/D Converters
9.4: All-Digital PLLs
9.5: Summary
Questions
References
Appendix A – Letter Symbols
Appendix B – Glossary
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