Advanced Signal Integrity for High-Speed Digital Designs | by Stephen H. Hall and Howard L. Heck | 2009 | ISBN: 9780470192351. Digital Engineers Resources. Electronics Design. Signal Integrity Design. CROSSTALK MINIMIZATION Techniques.
Advanced Signal Integrity for High-Speed Digital Designs
by Stephen H. Hall and Howard L. Heck
2009 (660 pages)
ISBN:9780470192351
Creating the optimal combination between theory and practical applications, this book is designed to provide contemporary readers with an understanding of the emerging high-speed signal integrity issues that are creating roadblocks in digital design.
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Advanced Signal Integrity for High-Speed Digital Designs
Preface
OVERVIEW
ACKNOWLEDGMENTS
Chapter 1 – Introduction—The Importance of Signal Integrity
1.1: COMPUTING POWER: PAST AND FUTURE
1.2: THE PROBLEM
1.3: THE BASICS
1.4: A NEW REALM OF BUS DESIGN
1.5: SCOPE OF THE BOOK
1.6: SUMMARY
ERRATA
REFERENCES
Chapter 2 – Electromagnetic Fundamentals for Signal Integrity
OVERVIEW
2.1: MAXWELL’S EQUATIONS
2.2: COMMON VECTOR OPERATORS
2.3: WAVE PROPAGATION
2.4: ELECTROSTATICS
2.5: MAGNETOSTATICS
2.6: POWER FLOW AND THE POYNTING VECTOR
2.7: REFLECTIONS OF ELECTROMAGNETIC WAVES
REFERENCES
PROBLEMS
Chapter 3 – Ideal Transmission-Line Fundamentals
3.1: TRANSMISSION-LINE STRUCTURES
3.2: WAVE PROPAGATION ON LOSS-FREE TRANSMISSION LINES
3.3: TRANSMISSION-LINE PROPERTIES
3.4: TRANSMISSION-LINE PARAMETERS FOR THE LOSS-FREE CASE
3.5: TRANSMISSION-LINE REFLECTIONS
3.6: TIME-DOMAIN REFLECTOMETRY
REFERENCES
PROBLEMS
Chapter 4 – Crosstalk
OVERVIEW
4.1: MUTUAL INDUCTANCE AND CAPACITANCE
4.2: COUPLED WAVE EQUATIONS
4.3: COUPLED LINE ANALYSIS
4.4: MODAL ANALYSIS
4.5: CROSSTALK MINIMIZATION
4.6: SUMMARY
REFERENCES
PROBLEMS
Chapter 5 – Nonideal Conductor Models
OVERVIEW
5.1: SIGNALS PROPAGATING IN UNBOUNDED CONDUCTIVE MEDIA
5.2: CLASSIC CONDUCTOR MODEL FOR TRANSMISSION LINES
5.3: SURFACE ROUGHNESS
5.4: TRANSMISSION-LINE PARAMETERS FOR NONIDEAL CONDUCTORS
REFERENCES
PROBLEMS
Chapter 6 – Electrical Properties of Dielectrics
OVERVIEW
6.1: POLARIZATION OF DIELECTRICS
6.2: CLASSIFICATION OF DIELECTRIC MATERIALS
6.3: FREQUENCY-DEPENDENT DIELECTRIC BEHAVIOR
6.4: PROPERTIES OF A PHYSICAL DIELECTRIC MODEL
6.5: FIBER-WEAVE EFFECT
6.6: ENVIRONMENTAL VARIATION IN DIELECTRIC BEHAVIOR
6.7: TRANSMISSION-LINE PARAMETERS FOR LOSSY DIELECTRICS AND REALISTIC CONDUCTORS
REFERENCES
PROBLEMS
Chapter 7 – Differential Signaling
OVERVIEW
7.1: REMOVAL OF COMMON-MODE NOISE
7.2: DIFFERENTIAL CROSSTALK
7.3: VIRTUAL REFERENCE PLANE
7.4: PROPAGATION OF MODAL VOLTAGES
7.5: COMMON TERMINOLOGY
7.6: DRAWBACKS OF DIFFERENTIAL SIGNALING
REFERENCE
PROBLEMS
Chapter 8 – Mathematical Requirements for Physical Channels
8.1: FREQUENCY-DOMAIN EFFECTS IN TIME-DOMAIN SIMULATIONS
8.2: REQUIREMENTS FOR A PHYSICAL CHANNEL
REFERENCES
PROBLEMS
Chapter 9 – Network Analysis for Digital Engineers
OVERVIEW
9.1: HIGH-FREQUENCY VOLTAGE AND CURRENT WAVES
9.2: NETWORK THEORY
9.3: PROPERTIES OF PHYSICAL S -PARAMETERS
REFERENCES
PROBLEMS
Chapter 10 – Topics in High-Speed Channel Modeling
10.1: CREATING A PHYSICAL TRANSMISSION-LINE MODEL
10.2: NONIDEAL RETURN PATHS
10.3: VIAS
REFERENCES
PROBLEMS
Chapter 11 – I/O Circuits and Models
OVERVIEW
11.1: I/O DESIGN CONSIDERATIONS
11.2: PUSH–PULL TRANSMITTERS
11.3: CMOS RECEIVERS
11.4: ESD PROTECTION CIRCUITS
11.5: ON-CHIP TERMINATION
11.6: BERGERON DIAGRAMS
11.7: OPEN-DRAIN TRANSMITTERS
11.8: DIFFERENTIAL CURRENT-MODE TRANSMITTERS
11.9: LOW-SWING AND DIFFERENTIAL RECEIVERS
11.10: IBIS MODELS
11.11: SUMMARY
REFERENCES
PROBLEMS
Chapter 12 – Equalization
OVERVIEW
12.1: ANALYSIS AND DESIGN BACKGROUND
12.2: CONTINUOUS-TIME LINEAR EQUALIZERS
12.3: DISCRETE LINEAR EQUALIZERS
12.4: DECISION FEEDBACK EQUALIZATION
12.5: SUMMARY
REFERENCES
PROBLEMS
Chapter 13 – Modeling and Budgeting of Timing Jitter and Noise
OVERVIEW
13.1: EYE DIAGRAM
13.2: BIT ERROR RATE
13.3: JITTER SOURCES AND BUDGETS
13.4: NOISE SOURCES AND BUDGETS
13.5: PEAK DISTORTION ANALYSIS METHODS
13.6: SUMMARY
REFERENCES
PROBLEMS
Chapter 14 – System Analysis Using Response Surface Modeling
14.1: MODEL DESIGN CONSIDERATIONS
14.2: CASE STUDY: 10-GB/S DIFFERENTIAL PCB INTERFACE
14.3: RSM CONSTRUCTION BY LEAST SQUARES FITTING
14.4: MEASURES OF FIT
14.5: SIGNIFICANCE TESTING
14.6: CONFIDENCE INTERVALS
14.7: SENSITIVITY ANALYSIS AND DESIGN OPTIMIZATION
14.8: DEFECT RATE PREDICTION USING MONTE CARLO SIMULATION
14.9: ADDITIONAL RSM CONSIDERATIONS
14.10: SUMMARY
REFERENCES
PROBLEMS
Appendix A – Useful Formulas, Identities, Units, and Constants
Appendix B – Four-Port Conversions between T-and S -Parameters
Appendix C – Critical Values of the F-Statistic
Appendix D – Critical Values of the T-Statistic
Appendix E – Causal Relationship between Skin Effect Resistance and Internal Inductance for Rough Conductors
Appendix F – Spice Level 3 Model for 0.25 µM Mosis Process
F-1: DEVICE MODELS
REFERENCE
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